One type of known memory device is the synchronous dynamic random access memory (SDRAM). A typical example of an SDRAM is shown in FIG. 1. The SDRAM 2 comprises two memory banks 4a and 4b. In some known SDRAMs, four memory banks are in fact provided. Each memory bank 4a and 4b contains a plurality of rows R which are sometimes referred to as pages. Each memory bank 4a and 4b also contains a plurality of columns C which intersect the rows R. A memory location is therefore identified by the bank number, the row number and the column number. To access a given memory location (or word) a memory interface unit 6 is provided. The memory interface unit 6 receives an input 7 which provides the address of the word to be accessed. The address identifies the memory bank, row and column of the word to be accessed.
Based on the address input to the memory interface unit 6, control signals 12 are generated which are output to a respective column control unit 8 and to a respective row control unit 10. Each bank 4a and 4b has its own row and column control units 8 and 10. The row and column control units 8 and 10 are sometimes referred to as row and column decoders respectively. The row control unit 10 will, in accordance with the address input to the memory interface unit, select a row R in the selected memory bank 4a or 4b. Once the row R or page has been selected (or opened), then the appropriate column C is selected by the column control unit 8, again in accordance with the input address.
The operation to open a page or row R will generally take several cycles. Once a page or row R has been opened, any word in that page or row R can be selected in one cycle. Thus a first word at a first column C location can be accessed in one cycle and a different word in that same row R but in a different column C location can be accessed in the next cycle. Once all the required accesses in a given row R or page have been completed, the open page or row R needs to be closed. This is achieved by the row control unit 10 precharging all the rows R including the selected row in the selected memory bank 4a or 4b to a given voltage. This closing operation must be completed before another page or row in the same bank can be selected or opened. This closing operation also takes several cycles.
Reference will now be made to FIG. 2 which shows a sequence of steps which occurs when eight words from a first selected row R in a first memory bank 4a are read and then eight words from a second selected row in the second memory bank 4b are read. As can be seen, the first six cycles A are used to open the first selected row R and read the first required word in that row of the first memory bank 4a. The next seven cycles B are used to read the remaining required seven words in the opened row R. The next three cycles D are required to close the first selected row R in the first bank 4a. The next six cycles E are used to open the second selected row R in the second memory bank 4b and read the first required word from that row. The next seven cycles F are required to read the other seven required words in the second selected row. The last three cycles G are required to close the second selected row R in the second memory bank 4b. Thus, in order to read eight words from a given row in a memory bank requires 16 cycles even though the reading operation itself only requires 8 cycles. This therefore reduces the efficiency of the memory device and increases the time required in order to complete read and write operations.
It is therefore an aim of embodiments of the present invention to reduce the number of cycles required to carry out an operation in respect of a memory having a plurality of memory regions.